NEW DELHI: India’s semiconductor ambitions are entering a more defined phase, with the government outlining a focused strategy around six core chip categories and setting a long-term target of manufacturing advanced 3-nanometre chips by 2032.
India’s push to build a domestic semiconductor ecosystem is being reshaped around a narrower set of priorities, as the government seeks to align chip design, manufacturing and industrial demand under a single framework. Speaking on Tuesday, Union Minister Ashwini Vaishnaw said the strategy would concentrate on six major categories of chips, with the aim of covering most of the country’s technology needs over the next decade.
The approach, he said, is intended to ensure that India develops “a complete semiconductor design ecosystem in a very comprehensive way,” while gradually expanding its manufacturing capabilities. The announcement comes as the government advances the second phase of its Design-Linked Incentive (DLI) Scheme and reviews progress made by domestic chip design firms selected under the programme.
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A Six-Pillar Focus for Chip Design
At the centre of the government’s plan is a focus on six types of chips: compute, radio frequency (RF), networking, power, sensor and memory. According to Mr. Vaishnaw, these categories form the building blocks for most modern electronic and digital products.
The government plans to encourage both academia and industry to develop new ideas and solutions within these areas. Officials view this as a way to create a broad base of intellectual property and design expertise, rather than concentrating only on a narrow slice of advanced processors.
Mr. Vaishnaw said that virtually every sector of the economy would require a combination or permutation of these six chip types, underscoring their relevance across consumer electronics, industrial systems, communications infrastructure and emerging technologies.
Design-Linked Incentives and Industry Participation
The six-category focus is being pursued under the second phase of the Design-Linked Incentive Scheme, which is designed to support domestic chip design companies through financial incentives and institutional backing. According to the minister, companies participating in the programme are expected to gain significant control over the development of technology products used in India.
The government estimates that chips designed and manufactured under this framework could account for 70 to 75 percent of applications currently used in the country. This figure reflects not only consumer devices such as smartphones and computers, but also a wide range of embedded systems and industrial applications.
Mr. Vaishnaw’s remarks followed a meeting with 24 chip design firms that have been selected under the DLI Scheme. The companies are engaged in developing designs across the six identified categories, with the government positioning design capabilities as a foundation that can be scaled into manufacturing over time.
Manufacturing Capacity and the 2029 Horizon
While advanced chip manufacturing remains a longer-term objective, the government has outlined nearer milestones for building capacity. Mr. Vaishnaw said that by 2029, India expects to have “a major capability of manufacturing and designing the chips” required for a large share of domestic applications.
Design, he noted, is already underway in several areas. Manufacturing, however, is expected to progress in stages, aligned with demand and technological readiness. Officials see this phased approach as a way to reduce dependence on imports while avoiding over-concentration on a single technology node too early in the process.
The emphasis on chips used in a majority of applications reflects a pragmatic focus on volume and relevance, rather than an immediate race to the most advanced manufacturing nodes.
The 3-Nanometre Target for 2032
Looking further ahead, the government has set a clear benchmark: achieving the capability to manufacture 3-nanometre chips by 2032. Such chips are currently used in high-end products, including modern smartphones and advanced computing systems.
“The level of 2032 is to reach 3-nanometer chips manufacturing and design,” Mr. Vaishnaw said, adding that while design work at advanced nodes is already being undertaken, manufacturing remains the key challenge. “Manufacturing we should reach 3 nanometer,” he said.
